CAN-CTRL

CAN 2.0，CAN FD和CAN XL总线控制器

CAN总线控制器有三个变体：2.0，FD和XL。2.0变体仅支持CAN 2.0规bob电子竞技俱乐部范，FD变体增加了对CAN FD的支持，并且XL变体支持CAN 2.0，CAN FD和CAN XL标准。

Each of the three core variants is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-B Ready. ASIL-C compatible versions can be made available and get certified upon request.

Verification

The core has been rigorously verified and has been production-proven multiple times.
It has been verified through extensive synthesis, place and route, simulation runs, Verification IP, and PlugFests. It has been embedded in several shipping customer products and is proven in both ASIC and FPGA technologies.

bob电子竞技俱乐部

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

可交付成果

核心包括成功实施所需的一切：

• VHDL or Verilog RTL source code
• Post-synthesis netlist
• Testbenches
  • 行为测试
  • 合成后验证
• Simulation scripts
• Synthesis scripts
• Linux driver
• Documentation, and RUVM register descriptions
• The optional safety-enhanced package includes the Safe-ty Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA) and the ASIL-B Ready certificate, issued by SGS-TÜV Saar GmbH.

可以将CAN-CTRL映射到任何ASIC技术或FPGA设备（提供足够的硅资源可用）。以下是配置三个接收缓冲区，三个发送缓冲区和三个接受过滤器的核心的样本结果（不包括优先级模式，TTCAN和CIA603时间戳）。

The next table provides sample results for the core config-ured with sixteen receive buffers, sixteen transmit buffers, sixteen acceptance filters, TTCAN, and 64-bit CiA603 timestamps,

Please contact CAST to get characterization data for your target configuration and technology.

The CAN-CTRL can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping).

注意：主机和可以限制为80MHz的时钟

When CAN XL support is added, the CAN-CTRL core occupies approximately 1,750 ALMs and requires 133k of memory bits.
Please contact CAST to get characterization data for your target configuration and technology.

The CAN-CTRL can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements.. The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include TTCAN, or CAN-XL).

CAN-CTRL参bob体育软件考设计已在各种技术中进行了评估。以下是针对三个接收缓冲区，三个发送缓冲区和三个接受过滤器（标准版本，无TTCAN）的面积优化的样本结果。

可以将CAN-CTRL映射到任何Xilinx FPGA设备（提供足够的硅资源可用）。以下是配置三个接收缓冲区，三个发送缓冲区和三个接受过滤器的核心的样本结果（不包括优先级模式，TTCAN和CIA603时间戳）。

注意：主机和可以限制为80MHz的时钟

When CAN XL support is added, the CAN-CTRL core occupies approximately 3,000 LUTs and 6.5 BRAM Tiles.
Please contact CAST to get characterization data for your target configuration and technology.