硅IP内核
CAN-CTRL
CAN 2.0,CAN FD和CAN XL总线控制器
Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications. It supports the original Bosch protocol and ISO specifications as defined in ISO 11898—including time-triggered operation (TTCAN) as specified in ISO 19898-4—and is also optimized to support the popular AUTOSAR and SAE J1939 specifications.
CAN协议使用多主总线配置进行网络节点之间的帧传输,并管理错误处理,而主机处理器上没有负担。核心使用户能够在各个组件之间建立经济和可靠的联系。它作为内存映射的I/O设备显示到主机处理器,该设备可访问CAN核心以控制帧的传输或接收。
The CAN-CTRL core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.
接收缓冲区的数量是合成时间可配置的。实现了两种类型的发射缓冲区:高优先级初级发射缓冲区(PTB)和较低优先级的二级发送缓冲区(STB)。PTB可以存储一条消息,而STB的随附的缓冲区插槽的数量为合成时间可配置。发送缓冲区可以在FIFO或优先级模式下运行。
核心实现了与飞利浦SJA1000相似的功能,其鹈鹕模式扩展功能提供了错误分析,诊断,系统维护和优化功能。
The CAN-CTRL is extensively verified, proven in several plugfests and a large number of production designs.
CAN总线控制器有三个变体:2.0,FD和XL。2.0变体仅支持CAN 2.0规bob电子竞技俱乐部范,FD变体增加了对CAN FD的支持,并且XL变体支持CAN 2.0,CAN FD和CAN XL标准。
Each of the three core variants is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-B Ready. ASIL-C compatible versions can be made available and get certified upon request.
Verification
The core has been rigorously verified and has been production-proven multiple times.
It has been verified through extensive synthesis, place and route, simulation runs, Verification IP, and PlugFests. It has been embedded in several shipping customer products and is proven in both ASIC and FPGA technologies.
bob电子竞技俱乐部
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
可交付成果
核心包括成功实施所需的一切:
- VHDL or Verilog RTL source code
- Post-synthesis netlist
- Testbenches
- 行为测试
- 合成后验证
- Simulation scripts
- Synthesis scripts
- Linux driver
- Documentation, and RUVM register descriptions
- The optional safety-enhanced package includes the Safe-ty Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA) and the ASIL-B Ready certificate, issued by SGS-TÜV Saar GmbH.
可以将CAN-CTRL映射到任何ASIC技术或FPGA设备(提供足够的硅资源可用)。以下是配置三个接收缓冲区,三个发送缓冲区和三个接受过滤器的核心的样本结果(不包括优先级模式,TTCAN和CIA603时间戳)。
配置 | Technology | 细胞区域 (eq. Gates) |
Memory Bits |
---|---|---|---|
CAN 2.0 | TSMC 40nm G | 10,800 | 1,088 |
CAN 2.0 | TSMC 28nm HPC | 8,600 | 1,088 |
CAN FD | TSMC 40nm G | 14,000 | 4,224 |
CAN FD | TSMC 28nm HPC | 10.441 | 4,224 |
CAN XL | TSMC 28nm HPC | 13,250 | 133,000 |
The next table provides sample results for the core config-ured with sixteen receive buffers, sixteen transmit buffers, sixteen acceptance filters, TTCAN, and 64-bit CiA603 timestamps,
配置 | Technology | 细胞区域 (eq. Gates) |
Memory Bits |
---|---|---|---|
CAN 2.0 | TTSMC 28nm HPC | 8,700 | 5,920 |
CAN 2.0 Safe | TTSMC 28nm HPC | 14,626 | 7,215 |
CAN FD | TTSMC 28nm HPC | 16,214 | 21,152 |
CAN FD Safe | TTSMC 28nm HPC | 39,714 | 25,779 |
Please contact CAST to get characterization data for your target configuration and technology.
The CAN-CTRL can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping).
Family Device | CAN 2.0 | can-fd | ||
---|---|---|---|---|
Logic | Memory | Logic | Memory | |
Max 10 10M50 |
2,343 LEs 0 MULTs |
1,088bits 3个RAM块 |
2,806 LEs 0 MULTs |
4,224 bits 3个RAM块 |
旋风v 5CEFA7 |
1,094 ALMs 1 DSP |
1,325 ALMs 1 DSP |
||
Cyclone 10 LP 10CL120 |
2,331 LEs 0 MULTs |
2,808 Les 0 MULTs |
||
Cyclone 10 GX 10ax115 |
1,072 ALMs 1 DSP |
1,317 ALMs 1 DSP |
||
Arria V GX 5AGXBB3 |
1,092施舍 1 DSP |
1,217 ALMs 1 DSP |
||
Arria 10 GX 10ax115 |
1,117 ALMs 1 DSP |
1,333施舍 1 DSP |
注意:主机和可以限制为80MHz的时钟
When CAN XL support is added, the CAN-CTRL core occupies approximately 1,750 ALMs and requires 133k of memory bits.
Please contact CAST to get characterization data for your target configuration and technology.
The CAN-CTRL can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements.. The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include TTCAN, or CAN-XL).
Family & Device | can-fdSupport | Logic | Block RAMs | 主机时钟(MHz) | CAN Clock (MHz) |
---|---|---|---|---|---|
ICE 40 u / P5k |
Yes | 3,883 LCS 544 PLBs |
6 | 42 | 25 |
ICE 40 u / P5k |
不 | 2,932 LCs 452 PLBs |
6 | 45 | 25 |
MachXO2 7000HC |
Yes | 1,530 Slices 3,025 LUT4s |
4 | 59 | 23 |
MachXO2 7000HC |
不 | 1,248 Slices 2,466 LUT4S |
0 | 62 | 29 |
ECP5 LFE5U-85F |
Yes | 1,810片 2,752 LUTs |
2 | 80 | 80 |
ECP5 LFE5U-85F |
不 | 1,444 Slices 2,135个Luts |
2 | 80 | 80 |
CAN-CTRL参bob体育软件考设计已在各种技术中进行了评估。以下是针对三个接收缓冲区,三个发送缓冲区和三个接受过滤器(标准版本,无TTCAN)的面积优化的样本结果。
Family | Variant | Logic Resources |
Memory Resources |
Freq. (MHz) |
---|---|---|---|---|
Igloo2 M2GL150-STD |
CAN 2.0 | 2,774 4LUT | 2 RAM1K18 | 60 |
Igloo2 M2GL150-STD |
CAN FD | 3,330 4LUT | 2 RAM1K18 | 60 |
PolarFire MPF500T-STD |
CAN 2.0 | 2,759 4LUT | 2 LSRAM | 100 |
PolarFire MPF500T-STD |
CAN FD | 3,375 4LUT | 2 LSRAM | 100 |
RTG4 RT4G150-STD |
CAN 2.0 | 2,711 4LUT | 2 RAM1K18 | 60 |
RTG4 RT4G150-STD |
CAN FD | 3,416 4LUT | 2 RAM1K18 | 60 |
SmartFusion2 M2S150-STD |
CAN 2.0 | 2,774 4LUT | 2 RAM1K18 | 60 |
SmartFusion2 M2S150-STD |
CAN FD | 3,330 4LUT | 2 RAM1K18 | 60 |
可以将CAN-CTRL映射到任何Xilinx FPGA设备(提供足够的硅资源可用)。以下是配置三个接收缓冲区,三个发送缓冲区和三个接受过滤器的核心的样本结果(不包括优先级模式,TTCAN和CIA603时间戳)。
Family Device | CAN 2.0 | can-fd | ||
---|---|---|---|---|
Logic | Memory | Logic | Memory | |
Artix-7 XC7A15T |
1,616 LUTs 511 Slices |
1,088bits 1 RAMB36 |
1,952 LUTs 652 Slices |
4,224 bits 1 RAMB36 |
Virtex-7 XCVX300T |
1,612 LUTs 522片 |
1,942 LUs 646 Slices |
||
Kintex UltraScale XCKU060 |
1,595 LUTs 240 CLB |
1,937 LUTs 296 CLB |
||
Kintex UltraScale+ xku15p |
1590 LUTs 264 CLBs |
1,941个Luts 337 CLBs |
注意:主机和可以限制为80MHz的时钟
When CAN XL support is added, the CAN-CTRL core occupies approximately 3,000 LUTs and 6.5 BRAM Tiles.
Please contact CAST to get characterization data for your target configuration and technology.
This product is sourced from Technology PartnerFraunhofer IPMS.
功能列表
CAN Specifications Support
- CAN 2.0&CAN FD(ISO 11898-11.2015,以及更早的ISO和Bosch规格)
- CAN XL (CiA 610-1 specification)
- TTCAN(ISO 11898-4 1级)
- 针对Autosar和SAE J1939优化
Enhanced Functionality
- Error Analysis features enabling diagnostics, system maintenance, and system optimization:
- Last error type
- 仲裁失去位置
- Error Warning Limit
- Listen-Only Mode enables CAN bus traffic analysis and automatic bit-rate detection
- Loop back mode for self-testing
- Time-stamping support, compliant to CiA's 603 specification
Flexible Message Buffering and Filtering
- Configurable number of:
- Receive buffers
- Lower-priority transmit buffers
- Independently programmable acceptance filters, 1 to 16
- One high-priority transmit buffer
- FIFO or priority mode for transmit buffers
易于使用和集成
- Programmable data rate up to 1 Mbit/s with CAN 2.0 and several Mbit/s with CAN FD or CAN XL option
- Programmable baud rate prescaler: 1 up to 1/256
- Single Shot Transmission Mode for lower software overhead and fast reloading of transmit buffer
- Programmable interrupt sources
- Generic 8-bit host-controller interface and optional 32-bit AMBA-APB or 32-bit AHB-Lite
- 单个主机可以通过可选的多罐装包装器控制多个CAN总线节点
Safety Enhanced Version (optional)
- ISO-26262 ASIL-B准备就绪
- Implements ECC for SRAM and spatial redundancy for inner logic protection
- ISO-26262 ASIL-C on request
Zero Risk
- Compatible with any CAN2.0 transceiver (PHY) that supports ISO-11898, and various CAN-FD PHYs from NXP, MicroChip, OnSemi, Infineon, etc.
- Multiple times production-proven
Efficient and Portable Design
- 可在RTL中提供,可用于ASIC和FPGA技术
验证IP
Available for this core:CAN-VIP
Resources
Resources
- 可以咬住时间计算器
- CAN in Automation (CiA) Knowledge Pages
- CIA CAN-XL SIG页面
- CANentry at Wikipedia
- CAN FDentry in Wikipedia
- NMEA 2000entry at Wikipedia
- DeviceNetentry at Wikipedia
- CANaerospacestandard documents
- CANaeropsaceentry in Wikipedia
- CAN Wiki
- The CANbus USAwebsite of the ESAcademy
- SAE J1939标准collection
- Autosar官方网站
- 向量Informatik的can页面
Partnerships
CAST is a member of theCAN in Automation (CiA)用户和制造商的贸易集团。